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Chapter-3, , Vv, , LOGIC GATES, , Introduction:, , Gate: A Gate is a simply an electronic circuit which operates on one or more input signals and, always produces an output signal., , Gates are digital (two state) circuits because the input and output signals are either low voltage (0) or, high voltage (1)., , Gates are often called logic circuits because they can be analyzed with Boolean algebra., , Gates are classified into two types:, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Logic gates, |, t +t, Basic Gates Derived Gates, fy fy es | Jf |, NOT AND OR NOR NAND XOR XNOR, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Basic Gates:, , NOT Gate:, , A NOT gate has only one input and one output., , The output state is always the opposite of the input state., , A NOT Gate is also called as Inverter gate, because the output is not same as the input., The output is sometimes called the complement (opposite) of the input., , The logical symbol and the truth tablz of NOT gate are given below., , , , , , , , x = 1, x X 0 1, I 0, , , , , , , , , , OR Gate:, , A OR gate has two or more input signal but only one output signal., , If any of the input signals is | (high), then the output is | (high)., , The logical symbol for two-input OR gate and the truth table is given below., , 1|Page

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F=X+ty, , , , , , , , xX F=X+¥, +, , >» AND Gate:, ¢ A AND gate has two or more input signal but only one output signal., , , , , , , , —|-lololx, -—\o|—jo|<, °, , , , , , , , © When all the input signals are | (high), the output is | (high), otherwise the output is 0., © The logical symbol for two-input AND gate and the truth table is given below., , , , , , , , , , , , , , X_]nYa|F=XyY, , x— F=X.Y 01.0 | 0, ae ae 0, , eS 1 0 0, m1 I, , , , , , , , , , , , , , > NOR Gate:, , ¢ ANOR gate has two or more input signal but only one output signal,, , ¢ The NOR gate is a complemented of OR gate., , © The output of NOR gate will be | only when all inputs are 0 and output will be 0 if any input, represents a 1., , e NOR is short form of NOT-OR., , © The symbol Jis used to represent a NOR operation. So Fan can be written as X NOR Y or X $, , ¢ The logical structure shows an OR gate and NOT gate. For input X and Y, the output of the Olu e, will be X+Y which is fed zs input to the NOT gate. So the output of NOR gate is given by 7, which is equal to X . ¥, , , , © The logical symbol for two-input NOR gate and the truth tabsyee given below., , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , [xy [Z]/F-., x roloto 1, rolo|t 0, Y o|i1i[0 0, x 7 pees oli1[t 0, 9 ; 1fo]|o 0, t—— rfolt 0, 0 1 0, 1 0 0 1 | 0 4. =, = 7 3 ee 0

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>, , , , NAND Gate:, , A NAND gate has two or more input signal but only one output signal., , The NAND gate is a complemented of AND gate., , The output of NAND gate will be 0 only when all inputs are | and output will be 0 if any input, represents a 0., , NAND is short form of NOT-AND., , ‘The symbol 4is used to represent a NOR operation. So i’ can be written as X NAND Y or X ty., lame logical structure shows an AND gate and NOT gate. For input X and Y, the output of the OR, geetie will be X .Y which is fed as input to the NOT gate. So the output of NAND gate is given by, , [NAY which is equal to X +¥, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , xX ¥ F= - x | ¥ Z FB = papers, 0 0 1 0 0 0 1, 0 | 1 0 0 1 |, | 0 1 0 1 0 1, an 0 ofift I, 1 0 0 1, 1 0 1 1, 1 1 0 1, > XOR (Exclusive-OR) Gate: Ley 0, , , , , , , , , , , , , , , , , , , , , , An exclusive-OR has two or more input signal but only one output signal., Exclusive-OR gate is different form of OR gate., Exclusive-OR gate produces output | for only those input combinations that have odd number of I’s., The output is 0 if there are even number of 1’s in the input., The output is | if there are odd number of 1’s in the input., In Boolean algebra, © sign stands for XOR operation. Thus X XOR Y can be written as XOY, If the output is given by:, F=XOY, , 3|Page

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F=X¥+Xy, e The XOR gate has a symbol similar to OR gate, except the additional curved line of the input side., , x 1 F=XOY=X¥+ XY, Y | ,, , ¢ The following truth table illustrates XOR operation for 2 and 3 inputs., , Number Input Output Number, Of I's xX Y |F=XOY of I’s ¥ F=XOYOZ, EVEN 0 0 0 EVEN 0, ODD ODD, ODD ODD, , EVEN EVEN, ODD, EVEN, EVEN, ODD, , , , > XNOR (Exclusive-NOR) Gate:, © The XNOR gate is complement of XOR gate., e The output of XNOR is | only when the logic values of both X and Y is same i.e. either both are, equal to | or both are 0., © Its output is 0 when its inputs are different., ¢ In Boolean algebra, @ sign stands for XNOR operation. Thus X XNOR Y can be written as X © Y, © Ifthe output is given by:, F=XOY, F=X¥ +f!", e The XNOR gate has a symbol similar to NOR gate, except the additional curved line of the input side., , X >) \ F=XOY=XY + XY, ¥, , e The following truth table illustrates XOR operation for 2 and 3 inputs., , Number, Of I's x, EVEN, , Number, of I's, EVEN, ODD, ODD, EVEN, ODD, EVEN, EVEN, ODD, , xX F=XOYOZ, , ODD 0, ODD 1, EVEN, , , , 4|Page

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Universal Gate (NAND & NOR):, , Universal gate is a gate using which all the basic gates can be designed., , NAND and NOR gate re called as Universal Gates, because all the Boolean functions can also be, implemented using these two gates., , NAND and NOR gates are more popular as these are less expensive and easier to design., Realization of all basic gates using NAND gate:, , NAND to NOT, In the figure we have two input NAND gatewehose inputs are purposely connected together so that, , the same input is applied to both., , fram RR =X, -y [————, , , , , , , , , , From the diagram X NAND X= KX, = K+X // DeMergan’s 2" Theorem, ~ x X+X=X, , = Inverted Input = NOT gate, NAND to AND, , In the figure we have two NAND gatessmmnnected so that the AND ommrations is performed., NAND gate 2 is used as a NOT gate., x 4, , Ya, , , , , , , , From the diagram X NAND Y_ =F1, , , , F2 =, = + Fi. / DeMorgan’s 2" Theorem, il X+X=K, , F2 = or, = AND gate, , NAND to OR:, The OR operation can be implemented using NAND gates connected as shown in figure, NAND gate 1 and NAND gate 2 are used as NOT to invert the inputs., , Fi=X, , | 3=KLY=X+Y, F.=¥