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Practical No. 1, Course : Digital Techniques, , Course Code: 22320, , Name of Student: ________________________________________________, Class: SYEJ, Roll No. ____________________________, Enrollment No. _____________________, Practical No.1: Test the functionality of logic gates., Practical Significance, Logic gates are the basic building block of all type of digital systems. Digital gates are, used in all digital circuits such as switches, memories, microprocessor, and embedded, systems. Knowledge of functions of logic gates will help the students to build the, digital circuits., Circuit Diagram:, For NOT Gate:
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For AND Gate:, , For OR Gate:
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For Ex-OR Gate:, , Observations and Calculations, 7404 ( NOT), , Inputs, , A, , LED, Status, (ON/OFF), , Output, voltage(v), , 0(0V), , ON, , 1, , 1(5V), , OFF, , 0, , 7408(AND), , 7432(OR), , 7486(EX-OR), , A, , B, , LED, Status, (ON/OFF), , Output, voltage, , LED, Status, (ON/OFF), , Output, voltage, , LED, Status, (ON/OFF), , Output, voltage, , 0(0V), , 0(0V), , OFF, , 0, , OFF, , 0, , OFF, , 0, , 0(0V), , 1(5V), , OFF, , 0, , ON, , 1, , ON, , 1, , 1(5V), , 0(0V), , OFF, , 0, , ON, , 1, , ON, , 1, , 1(5V), , 1(5V), , ON, , 1, , ON, , 1, , OFF, , 0
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Interpretation of Results:, 1., 2., 3., 4., , For NOT Gate output is high when input is low and vice versa., For AND Gate output is high when both inputs are high., For OR Gate output is high when any one input or both inputs are high., For Ex-OR Gate output is high when both inputs are dissimilar., , Conclusions & Recommendation, Based on the observation table, each truth table shows how unique each gate is. Furthermore, the, different gates work in their own ways. For instance an AND gate requires both input to be 1 in, order to function the circuit. For OR gate requires at least one input to be 1 in order to function, the circuit. NOT gate gives the inverted output. Ex-OR gate shows the dissimilarity of inputs,, when both inputs are dissimilar output turns High
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Practical No. 2, Course : Digital Techniques, , Course Code: 22320, , Name of Student: ________________________________________________, Class: SYEJ, Roll No. ____________________________, Enrollment No. _____________________, Practical No.2: Test the functionality of universal logic gates., Practical Significance, A universal gate is a gate which can implement any Boolean function without need to use any, other gate type. In practice, this is advantageous since NAND and NOR gates are economical, and easier to fabricate and are the basic gates used in all IC digital logic families., , Circuit Diagram:, For NAND Gate:, , For NOR Gate:
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Observations and Calculations, Inputs, , 7400(NAND), , 7402(NOR), , A, , B, , LED, Status, (ON/OFF), , Output, voltage, , LED, Status, (ON/OFF), , Output, voltage, , 0(0V), , 0(0V), , OFF, , 1, , ON, , 1, , 0(0V), , 1(5V), , OFF, , 1, , OFF, , 0, , 1(5V), , 0(0V), , OFF, , 1, , OFF, , 0, , 1(5V), , 1(5V), , ON, , 0, , OFF, , 0, , Interpretation of Results:, 1. For NAND Gate output is high when at least one input or both inputs are low., 2. For NOR Gate output is high when both inputs are low., Conclusions & Recommendation, In conclusion, a NAND gate is an inverted AND gate, and a NOR gate is an inverted OR gate., The output of a two input NOR gate is low, when either one or both inputs are “High”. In, Comparison, The output of a two input NAND gate is high, when either one or both inputs are, “LOW”.
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Practical No. 3, Course : Digital Techniques, , Course Code: 22320, , Name of Student: ________________________________________________, Class: SYEJ, Roll No. ____________________________, Enrollment No. _____________________, , Practical No.3: Construct basic gates using universal gates., Practical Significance, A universal gate is a gate which can implement any Boolean function without need to use any, other gate type. The NAND and NOR gates are universal gates. In practice, this is, advantageous since NAND and NOR gates are economical and easier to fabricate and are, the basic gates used in all IC digital logic families., , Circuit Diagram:, NOT gate Using NAND:, , OR gate Using NAND:
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AND gate Using NAND:, , NOT gate Using NOR:, , AND gate Using NOR:
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OR gate Using NOR:, , Observations and Calculations, For NOT Gate using IC 7400, NOT, A, , LED, Status, (ON/OFF), , Output, voltage(v), , 0(0V), , OFF, , 1, , 1(5V), , ON, , 0, , For AND Gate/OR Gate using IC 7400, Inputs, , AND, , A, , B, , LED Status, (ON/OFF), , Output, voltage, , OR, LED Status, (ON/OFF), , 0(0V), , 0(0V), , OFF, , 0, , OFF, , 0, , 0(0V), , 1(5V), , OFF, , 0, , ON, , 1, , 1(5V), , 0(0V), , OFF, , 0, , ON, , 1, , 1(5V), , 1(5V), , ON, , 1, , ON, , 1, , For NOT Gate using IC 7402, NOT, A, , LED, Status, (ON/OFF), , Output, voltage(v), , 0(0V), , OFF, , 1, , 1(5V), , ON, , 0, , Output, voltage
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For AND Gate/OR Gate using IC 7402, Inputs, , AND, , A, , B, , LED Status, (ON/OFF), , Output, voltage, , OR, LED Status, (ON/OFF), , 0(0V), , 0(0V), , OFF, , 0, , OFF, , 0, , 0(0V), , 1(5V), , OFF, , 0, , ON, , 1, , 1(5V), , 0(0V), , OFF, , 0, , ON, , 1, , 1(5V), , 1(5V), , ON, , 1, , ON, , 1, , Output, voltage, , Interpretation of Results:, Based on the observation table, each truth table shows, universal gates performs functions of all, basic gates. i.e. NAND gate functions as NOT gate, NAND gate functions as AND gate, NAND, gate functions as OR gate, NOR gate functions as NOT gate, NOR gate functions as AND gate,, NOR gate functions as OR gate,, Conclusions & Recommendation, To configure a NAND or NOR gate to function like an inverter, connect both the inputs together., A NAND gate is an inverted AND gate, to configure AND using NAND output of NAND is, inverted using NAND as NOT. A NOR gate is an inverted OR gate, to configure OR using NOR, output of NOR is inverted using NOR as NOT.
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Practical No. 4, Course : Digital Techniques, , Course Code: 22320, , Name of Student: ________________________________________________, Class: SYEJ, Roll No. ____________________________, Enrollment No. _____________________, , Practical No. 4: Verify De morgan’s theorems., Practical Significance, Logic gates are the basis units to implement complex logic functions. De Morgan's Theorems, are used to simplifies the complex Boolean/Logic functions. This practical will enable the, students to use De Morgan's theorem to simplify the complex function for the efficient, hardware implementation., , Circuit Diagram:, De Morgan’s First Theorem:, , De Morgan’s Second Theorem:
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Practical No. 5, Course : Digital Techniques, , Course Code: 22320, , Name of Student: ________________________________________________, Class: SYEJ, Roll No. ____________________________, Enrollment No. _____________________, , Practical No. 5: Design half Adder and half Subtractor using Boolean, expression., Practical Significance, Digital computers perform variety of information tasks. Among the functions, encountered is the various arithmetic operations, the most basic arithmetic operation is, the addition or subtraction of two binary digits. A binary adder-subtractor is a, combinational circuit that performs the arithmetic operations of addition and, subtraction with binary numbers., Circuit Diagram:, Half Adder:, , Half Subtractor:
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Observations and Calculations:, For Half Adder:, , Inputs, A, 0, 0, 1, 1, , Outputs, C, , Sum, , Carry, , 0, 1, 0, 1, , 0, 1, 1, 0, , 0, 0, 0, 1, , For Half Subtractor:, , Inputs, A, 0, 0, 1, 1, , Outputs, C, , Difference, , Borrow, , 0, 1, 0, 1, , 0, 1, 1, 0, , 0, 1, 0, 0, , Interpretation of Results:, , Conclusions & Recommendation
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Practical No. 6, Course : Digital Techniques, , Course Code: 22320, , Name of Student: ________________________________________________, Class: SYEJ, Roll No. ____________________________, Enrollment No. _____________________, , Practical No. 6: Design Full Adder and full subtractor., Practical Significance, Digital computers perform variety of information tasks. Among the functions, encountered are the various arithmetic operations. The most basic arithmetic operation, is the addition or subtraction of binary digits. A binary adder-subtractor is a, combinational circuit that performs the arithmetic operations of addition and, subtraction with binary numbers. In this practical, students will build circuit and, perform addition and subtraction of 3 bits., Circuit Diagram:, Full Adder:
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Full Subtractor:, , Observations and Calculations:, For Adder:, , Inputs, A, , Outputs, , B, , C, , Sum, , Carry, , 0, 0, 0, 0, , 0, 0, 1, 1, , 0, 1, 0, 1, , 0, 1, 1, 0, , 0, 0, 0, 1, , 1, , 0, , 0, , 1, , 0, , 1, , 0, , 1, , 0, , 1, , 1, , 1, , 0, , 0, , 1, , 1, , 1, , 1, , 1, , 1
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For Subtractor:, , Inputs, A, , Outputs, , B, , C, , Difference, , Borrow, , 0, 0, 0, 0, , 0, 0, 1, 1, , 0, 1, 0, 1, , 0, 1, 1, 0, , 0, 1, 1, 1, , 1, , 0, , 0, , 1, , 0, , 1, , 0, , 1, , 0, , 0, , 1, , 1, , 0, , 0, , 0, , 1, , 1, , 1, , 1, , 1, , Interpretation of Results:, , Conclusions & Recommendation
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Practical No. 7, Course : Digital Techniques, , Course Code: 22320, , Name of Student: ________________________________________________, Class: SYEJ, Roll No. ____________________________, Enrollment No. _____________________, , Practical No. 7: Construct and test BCD to 7 segment decoder using IC 7447., Practical Significance, Practical Significance: BCD is an abbreviation for binary-coded decimal. A Digital, Decoder IC, is a device which converts one digital format into another and one of the, most commonly used devices for doing this is called the BCD to 7-Segment Display, Decoder. It is used to display decimal numbers., Circuit Diagram:
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Observations and Calculations:, , Data Input, , Output, Display, Output, , D, , C, , B, , A, , a, , b, , c, , d, , e, , f, , g, , 0, 0, 0, 0, 0, 0, , 0, 0, 0, 0, 1, 1, , 0, 0, 1, 1, 0, 0, , 0, 1, 0, 1, 0, 1, , 0, 1, 0, 0, 1, 0, , 0, 0, 0, 0, 0, 1, , 0, 0, 1, 0, 0, 0, , 0, 1, 0, 0, 1, 0, , 0, 1, 0, 1, 1, 1, , 0, 1, 1, 1, 0, 0, , 1, 1, 0, 0, 0, 0, , 0, 1, 2, 3, 4, 5, , 0, , 1, , 1, , 0, , 1, , 1, , 0, , 0, , 0, , 0, , 0, , 6, , 0, , 1, , 1, , 1, , 0, , 0, , 0, , 1, , 1, , 1, , 1, , 7, , 1, , 0, , 0, , 0, , 0, , 0, , 0, , 0, , 0, , 0, , 0, , 8, , 1, , 0, , 0, , 1, , 0, , 0, , 0, , 1, , 1, , 0, , 0, , 9, , Interpretation of Results:, , Conclusions & Recommendation
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Practical No. 8, Course : Digital Techniques, , Course Code: 22320, , Name of Student: ________________________________________________, Class: SYEJ, Roll No. ____________________________, Enrollment No. _____________________, Practical No. 8: Verify operation of Multiplexer (MUX)., Practical Significance, In most of the electronic systems, the digital data is available on more than one line. It, is necessary to route this data over a single line. Under such circumstances we require a, circuit which selects one of the many inputs at a time. This circuit is a multiplexer,, which has many inputs, one output and some select inputs. Multiplexer improves the, reliability of the digital system because it reduces the number of external wired, connections., Circuit Diagram:
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Observations and Calculations:, Strobe, Input, , Data, Input, , G, , Din, , S2, , S1, , S0, , Y, , 0, 0, 0, 0, 0, 0, , D0 = 1, D0 = 0, D1 = 1, D1 = 0, D2 = 1, D2 = 0, , 0, 0, 0, 0, 0, 0, , 0, 0, 0, 0, 1, 1, , 0, 0, 1, 1, 0, 0, , 1, 0, 1, 0, 1, 0, , 0, , D3 = 1, , 0, , 1, , 1, , 1, , 0, , 0, , D3 = 0, , 0, , 1, , 1, , 0, , 1, , 0, , D4 = 1, , 1, , 0, , 0, , 1, , 0, , 0, , D4 = 0, , 1, , 0, , 0, , 0, , 1, , 0, , D5 = 1, , 1, , 0, , 1, , 1, , 0, , 0, , D5 = 0, , 1, , 0, , 1, , 0, , 1, , 0, , D6 = 1, , 1, , 1, , 0, , 1, , 0, , 0, , D6 = 0, , 1, , 1, , 0, , 0, , 1, , 0, , D7 = 1, , 1, , 1, , 1, , 1, , 0, , 0, , D7 = 0, , 1, , 1, , 1, , 0, , 1, , 1, , X, , X, , X, , X, , 0, , 1, , Select Input, , Interpretation of Results:, , Conclusions & Recommendation, , Output, , ̅, 𝑌, , 0, 1, 0, 1, 0, 1
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Practical No. 9, Course : Digital Techniques, , Course Code: 22320, , Name of Student: ________________________________________________, Class: SYEJ, Roll No. ____________________________, Enrollment No. _____________________, , Practical No. 9: Functionality of Demultiplexers., Practical Significance, A demultiplexer (or demux) is a device taking a single input signal and selecting one of, many data-output-lines, which is connected to the single input. An electronic, demultiplexer can be considered as a single-input, multiple-output switch., Demultiplexers are mainly used in Boolean function generators and decoder circuits., Circuit Diagram:
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Observations and Calculations:, , Interpretation of Results:, , Conclusions & Recommendation, , 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, , 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, , 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, , 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, , 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, , 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, , 5, , 4, , 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, , Y1, , 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, , 3, , 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, , Y1, , 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, , 2, , Y9, , 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, , Y1, , Y8, , 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, , 1, , Y7, , 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, , Y1, , Y6, , 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, , 0, , Y5, , 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, , Y1, , Y4, , 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, , Y1, , Y3, , S0, , 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, X, , Y2, , 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, X, , Y1, , 1, 1, 1, 1, 1, 1, 1, 1, X, , 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, X, , Y0, , 0, 0, 0, 0, 0, 0, 0, 0, , Outputs, S1, , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, , S2, , G, , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, , S3, , Din, , Inputs
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Practical No. 10, Course : Digital Techniques, , Course Code: 22320, , Name of Student: ________________________________________________, Class: SYEJ, Roll No. ____________________________, Enrollment No. _____________________, , Practical No.10: Test functionality of RS Flip flop using NAND gates., Practical Significance, A flip-flop is a circuit that has two stable states and can be used to store information. A, flip flop is a bistable multivibrator. The circuit can be made to change state by signals, applied to one or many control inputs and will have one or two outputs. The flip flop is, a one bit memory cell it stores one bit of information. The data available in memory can, be used for further operation. The flip flops are used in bounce elimination switch, shift, registers, counters and in random access memory., Circuit Diagram:, , Observations and Calculations:, , Inputs, , Outputs, Comment, , 1, , ̅, 𝑸, , 0, , No Change, , 0, , 1, , Preset, , S, , R, , Q, , 0, , 0, , 0, , 1
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Inputs, , Outputs, Comment, , 1, , ̅, 𝑸, , 0, , Set, , 1, , 1, , Invalid, , S, , R, , Q, , 1, , 0, , 1, , 1, , Interpretation of Results:, , Conclusions & Recommendation
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Practical No. 11, Course : Digital Techniques, , Course Code: 22320, , Name of Student: ________________________________________________, Class: SYEJ, Roll No. ____________________________, Enrollment No. _____________________, , Practical No.11: Test functionality of MS JK Flip flop., Practical Significance, The limitation of SR flip flop is over come in JK flip flop. In JK flip flop when J=K=1,, the output is uncertain; this situation is called Race around condition. To avoid the, problem of race around condition the JK flip flop in Master and slave mode is used., Circuit Diagram:, , Observations and Calculations:, Input, , Outputs, , ̅̅̅̅̅, 𝑷𝑹, , ̅𝑪𝑹, ̅̅̅̅, , CLK, , J, , K, , Q, , 0, , X, , X, , X, , 1, , 0, , 1, , 0, , X, , X, , 1, , 0, , 0, , X, , 1, , 1, , ↓, , 1, , 1, , 1, 1, , 0, , ̅, 𝑸, , Comment, , 1, , Prohibited, , 1, , 0, , Preset, , X, , 0, , 1, , Clear, , 0, , 0, , Q, , No Change, , ↓, , 0, , 1, , 0, , ̅, 𝑸, , 1, , Reset, , 1, , ↓, , 1, , 0, , 1, , 0, , Set, , 1, , ↓, , 1, , 1, , ̅, 𝑸, , Q, , Toggle
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Interpretation of Results:, , Conclusions & Recommendation
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Practical No. 12, Course : Digital Techniques, , Course Code: 22320, , Name of Student: ________________________________________________, Class: SYEJ, Roll No. ____________________________, Enrollment No. _____________________, , Practical No.12: Test functionality of D and T Flip flop., Practical Significance, D Flip —Flop (Delay Flip —Flop) is used to provide time delay. They are basic, building blocks of Shift Registers T Flip-Flop (Toggle Flip-Flop) experiences a change, in output in each clock edge. Hence it can be used as a frequency divider. T Flip-Flop, can also be used to design Counters., Circuit Diagram:
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Observations and Calculations:, For D Flip Flop:, Input, ̅̅̅̅̅, 𝑷𝑹, , 0, , 0, 1, 1, 1, , ̅𝑪𝑹, ̅̅̅̅, , 0, 1, 0, 1, 1, , Outputs, CLK, , D, , Q, , X, X, X, ↓, ↓, , X, X, X, 0, 1, , 1, 1, 0, 0, 1, , ̅, 𝑸, , Comment, , 1, 0, 1, 1, 0, , Prohibited, Preset, Clear, No Change, D=Q, , ̅, 𝑸, , Comment, , For T Flip Flop:, Input, ̅̅̅̅̅, 𝑷𝑹, , 0, , 0, 1, 1, 1, , ̅𝑪𝑹, ̅̅̅̅, , 0, 1, 0, 1, 1, , Outputs, CLK, , T, , Q, , X, X, X, ↓, ↓, , X, X, X, 0, 1, , 1, 1, 0, 0, 1, , Interpretation of Results:, , Conclusions & Recommendation, , 1, 0, 1, 1, 0, , Prohibited, Preset, Clear, No Change, Toggle
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Practical No. 13, Course : Digital Techniques, , Course Code: 22320, , Name of Student: ________________________________________________, Class: SYEJ, Roll No. ____________________________, Enrollment No. _____________________, , Practical No.13: 4 bit Ripple counter., Practical Significance, Counter is a sequential circuit used for counting the number of clock pulses. It is a, group of Flip-Flops with a clock signal applied to it. A counter has natural count of 2n, where "n" is number of flip-flops in the counter. A 4-bit counter has 16 states., Circuit Diagram:, , Observations and Calculations:, , Input, No. of Clock, Pulses, , 0, 1, 2, 3, 4, 5, 6, , 7, 8, 9, , Outputs, Q3, , Q2, , Q1, , Q0, , 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, , 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, , 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, , 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, , Decimal, Equivalent, , 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
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Input, No. of Clock, Pulses, , 10, 11, 12, 13, 14, 15, 16, , Outputs, Q3, , Q2, , Q1, , Q0, , 1, 1, 1, 1, 1, 1, 0, , 0, 0, 1, 1, 1, 1, 0, , 1, 1, 0, 0, 1, 1, 0, , 0, 1, 0, 1, 0, 1, 0, , Interpretation of Results:, , Conclusions & Recommendation, , Decimal, Equivalent, , 10, 11, 12, 13, 14, 15, 0
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Practical No. 14, Course : Digital Techniques, , Course Code: 22320, , Name of Student: ________________________________________________, Class: SYEJ, Roll No. ____________________________, Enrollment No. _____________________, , Practical No.14: Decade counter Using IC 7490., Practical Significance, Counter is a sequential circuit used for counting the number of clock pulses. It is a, group of Flip-Flops with a clock signal applied to it. A counter has natural count of 2n, where "n" is number of flip-flop in the counter. Decade counter is a counter which has, ten states from 0 to 9., Circuit Diagram:, , Observations and Calculations:, Input, No. of Clock, Pulses, , 0, 1, 2, 3, 4, 5, , Outputs, QA, , QB, , QC, , QD, , 0, 0, 0, 0, 0, 0, , 0, 0, 0, 0, 1, 1, , 0, 0, 1, 1, 0, 0, , 0, 1, 0, 1, 0, 1, , Decimal, Equivalent, , 0, 1, 2, 3, 4, 5
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Input, No. of Clock, Pulses, 6, , 7, 8, 9, 10, , Outputs, QA, , QB, , QC, , QD, , 0, 0, 1, 1, 0, , 1, 1, 0, 0, 0, , 1, 1, 0, 0, 0, , 0, 1, 0, 1, 0, , Interpretation of Results:, , Conclusions & Recommendation, , Decimal, Equivalent, , 6, 7, 8, 9, 0
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Practical No. 15, Course : Digital Techniques, , Course Code: 22320, , Name of Student: ________________________________________________, Class: SYEJ, Roll No. ____________________________, Enrollment No. _____________________, , Practical No.15: 4 Bit Universal Shift Register., Practical Significance, Universal Shift Register is a register which can be configured to load and/or retrieve the, data in any mode (either serial or parallel) by shifting it either towards right or towards, left. In other words, a combined design of unidirectional (either right- or left-shift of, data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift register along, with parallel load provision is referred to as universal shift register., Circuit Diagram:
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Observations and Calculations:, Mode Control, S1, 0, 1, 0, 1, , CLK, , ↑, ↑, ↑, ↑, ↑, ↑, ↑, , Mode Control, S1, S0, , 1, 1, 1, 1, 1, 1, 1, , State, , S0, 0, 0, 1, 1, , 1, 1, 1, 1, 1, 1, 1, , Hold, Shift Left, Shift Right, Parallel Load, , A, , Inputs, B, C, , D, , QA, , 1, 1, 1, 1, 0, 0, 0, , 0, 1, 1, 1, 1, 0, 0, , 0, 0, 0, 1, 1, 1, 1, , 1, 1, 1, 1, 0, 0, 0, , Interpretation of Results:, , Conclusions & Recommendation, , 0, 0, 1, 1, 1, 1, 0, , Outputs, QB, QC, , 0, 1, 1, 1, 1, 0, 0, , 0, 0, 1, 1, 1, 1, 0, , QD, , 0, 0, 0, 1, 1, 1, 1
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Practical No. 16, Course : Digital Techniques, , Course Code: 22320, , Name of Student: ________________________________________________, Class: SYEJ, Roll No. ____________________________, Enrollment No. _____________________, , Practical No.16: R-2R Resistive Network., Practical Significance, A digital to analog converter (DAC) is a circuit that converts digital numbers into, analog voltage or current output. R-2R ladder is a resistive network of which output, voltage is a properly weighted sum of the digital inputs. With this experiment you will, get an exposure to R-2R network which is used in digital to analog converters., Circuit Diagram:, , Observations and Calculations, , Inputs, , R-2R Ladder DAC, Theoretical (V), , D3, , D2, , D1, , D0, , 0, , 0, , 0, , 0, , 0, , 0, , 0, , 0, , 0, , 0, 0, , Vo = Vref [, , 𝐷0 𝐷1 𝐷2 𝐷3, +, +, +, ], 16, 8, 4, 2, , Practical (V), , 0, , 0, , 1, , 0.3125, , 0.3, , 1, , 0, , 0.625, , 0.6, , 0, , 1, , 1, , 0.935, , 1, , 1, , 0, , 0, , 1.25, , 1.3
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Inputs, , R-2R Ladder DAC, Theoretical (V), , D3, , D2, , D1, , D0, , 0, , 1, , 0, , 1, , 0, , 1, , 1, , 0, , 1, , 1, , Vo = Vref [, , 𝐷0 𝐷1 𝐷2 𝐷3, +, +, +, ], 16, 8, 4, 2, , Practical (V), , 1.5625, , 1.6, , 0, , 1.875, , 1.6, , 1, , 1, , 2.1875, , 2, , 0, , 0, , 0, , 2.5, , 2.6, , 1, , 0, , 0, , 1, , 2.81, , 3, , 1, , 0, , 1, , 0, , 3.125, , 3.3, , 1, , 0, , 1, , 1, , 3.4375, , 3.7, , 1, , 1, , 0, , 0, , 3.75, , 4.3, , 1, , 1, , 0, , 1, , 4.0625, , 4.7, , 1, , 1, , 1, , 0, , 4.375, , 4.8, , 1, , 1, , 1, , 1, , 5.4, , 5.1, , Interpretation of Results:, , Conclusions & Recommendation
